1. Field of the Invention
The present invention relates to processing apparatuses and methods for processing IP (Internet Protocol) packets.
2. Description of the Related Art
In protocol processing, one type of processing that involves a large amount of processor processing is IP reassembly. In IP communications, an IP packet is transmitted by fragmenting it into a plurality of IP packets at a sender or on a transmission path, and received by recovering the fragmented original packet at a receiver. The processing of transmitting an IP packet by fragmenting it into a plurality of IP packets is called IP fragmentation. The processing of receiving the fragmentary IP packets and recovering the original IP packet is called IP reassembly. Specifications for IP reassembly are available in RFC 791.
Two algorithms for IP reassembly are known, namely, a procedure described in RFC 791 and a procedure described in RFC 815. Herein, the former procedure will be introduced. It is to be noted that the former IP reassembly procedure will be herein referred to as a bitmap table scheme.
In IP reassembly according to the bitmap table scheme, a receiver prepares bit tables in which every 8 octets of payload data of a sender's IP packet are assigned to one bit. Since the maximum length of an IP datagram is 65535 octets, a prepared bit table requires a length of about 8 kilobits. While payload data of each arriving fragment packet is saved, the reception state of fragment data is managed by setting bits in the bit table corresponding to the offset position and length of the fragment data. Thereafter, when all the bits in the bit table corresponding to the payload length of the sender's IP packet are set, which means that data needed for reassembling the fragmented original IP packet has all been arrived, the IP reassembly processing is completed.
In recent years, network communications have rapidly become faster, and Ethernet® products compatible with gigabit networks have already been popular for consumer use. Further, the IEEE 802.3 working group is currently going to establish a standard that can achieve a transmission speed of 40 megabits/s or 100 megabits/s. With such speedups in network communications, applications using IP communications and the amount of transmitted and received data are both increasing. Therefore, load for communication protocol processing is increasingly imposed on communication terminal devices.
Conventionally, protocol processing for IP communications is often implemented in software called the TCP/IP (Transmission Control Protocol/Internet Protocol) protocol stack. Also in embedded devices having an IP communication capability, IP protocol processing is often software-implemented. However, small embedded devices are often equipped with a low operation frequency CPU, which is advantageous in terms of the manufacturing cost and the amount of power consumption. This increases the processor load for required software-implemented protocol processing.
Thus, it has become difficult with the conventional processing to achieve a high communication performance. A further problem is that sufficient CPU resources cannot be allocated to application processing due to the processing load for communication processing.
As a measure for these problems, a technique generally called TOE (TCP/IP Offload Engine) exists for reducing the communication processing load on the processor and realizing high-speed IP communications. This TOE is a technique for speeding up the TCP/IP protocol processing by using processing unit separate from the processor that executes applications.
In TOE, all or part of the protocol processing is often performed in hardware processing (an integrated circuit) to achieve a high speed. Implementations for embedded devices may include embodying TOE in an LSI and containing it in a chip.
In the above-described IP reassembly according to the bitmap table scheme, the size of a table required for accommodating the maximum packet size of an unfragmented IP packet is 1 Kbyte (8192 bits). Also, bit tables as many as the number of concurrent IP reassembly processes processed in parallel are necessary. As the number of received IP packets per unit time increases due to speedups in communications, the number of IP reassembly processes processed in parallel also increases, so that the memory size required for the bit tables increases.
To realize high-speed IP reassembly in hardware processing by the above-described TOE technique, it is desirable to form the bit tables in on-chip memory, which involves a small access delay. However, a large memory capacity that matches the number of processes processible in parallel is required, and the use of high-cost on-chip memory will increase the memory cost. On the contrary, small-capacity memory will pose a problem in that the number of processes processible in parallel is limited.
A conventional art for managing the arrival state of fragment data by using this bit data is Japanese Patent Laid-Open No. 2007-274056, for example. In Japanese Patent Laid-Open No. 2007-274056, the fragmentation size of IP fragments is limited to a small range to give an implicit fragment number to each fragment packet, so that management of the reception state of the fragment packets is simplified and a high speed is achieved.
In this method, since the size to which an IP packet is fragmented is predefined, the bit width for managing the reception state of fragment packets can be smaller than 8 Kbits. Therefore, the memory size required for IP reassembly can be reduced. However, this method is not suitable for performing IP reassembly of arbitrary-sized fragment packets because the fragmentation size is limited to the small range.